This one is a bit of a mixed bag. Two days ago, I had quite a successful night. The SPI controller I've been working on performed great after fixing a few implementation issues that were uncovered in the course of live testing.
Also interesting was that the testing "UI" I made (in reality 8 LEDs and 16 rocker-style DIP switches) allowed not just for a static test but instead for reading and writing at will with user-specified data and a user-specified memory page address. Since I didn't have a lot of switches available and I was using one cluster of 8 solely for control signals, only the lowest 8 bits of the address were user-adjustable, but still...that's 256 pages (2 Kb) available for playing with for just a test. =D
Yesterday I eliminated the last cycle of controller overhead latency present in the main course of SPI cycles themselves. Or, in other words, the controller can now properly do SPI waveforms as tight as 1 cycle high and 1 cycle low without distorting the wave by stretching either side of that out due to control logic needing extra cycles.
This is the sort of difference it can make. The transaction time is down to 360ns versus the original 520ns at 50 MHz since each SPI cycle takes only two controller cycles instead of three.
That brings us to the roadblock. I'm using a 10 MHz crystal XO and went to instantiate a DCM for the 50 MHz signal. I could use a 50 MHz XO, but it causes interference on my TV. XST crashes during compilation with the DCM in there. Go figure. I'm asking Xilinx for help on this one since I know the Spartan 6 LX9 I'm using has 4 DCMs available in it.
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